Woojin Rim

According to our database1, Woojin Rim authored at least 13 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit.
IEEE J. Solid State Circuits, 2022

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
IEEE J. Solid State Circuits, 2019

2018
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization.
IEEE J. Solid State Circuits, 2017

12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 14 nm FinFET 128 Mb SRAM With V<sub>MIN</sub> Enhancement Techniques for Low-Power Applications.
IEEE J. Solid State Circuits, 2015

2014
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics.
IEEE Trans. Circuits Syst. II Express Briefs, 2012


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