Tae Woo Oh

Orcid: 0000-0002-7545-2429

Affiliations:
  • Yonsei University, Seoul, South Korea


According to our database1, Tae Woo Oh authored at least 19 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

2023
Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist.
IEEE Trans. Circuits Syst. II Express Briefs, 2023

2022
SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.
IEEE J. Solid State Circuits, 2022

2021
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation.
IEEE Access, 2021

Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells.
IEEE Access, 2021

High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops.
IEEE Access, 2021

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM.
IEEE Access, 2021

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

2019
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
IEEE J. Solid State Circuits, 2019

2018
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Power-Gated 9T SRAM Cell for Low-Energy Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2016


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