Dimitrios Velenis

According to our database1, Dimitrios Velenis authored at least 34 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor.
IEEE Trans. Very Large Scale Integr. Syst., 2022

(Why do we need) Wireless Heterogeneous Integration (anyway?).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules.
Proceedings of the European Conference on Optical Communication, 2021

2019
Fabrication Cost Analysis for Contactless 3-D ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Process Complexity and Cost Considerations of Multi-Layer Die Stacks.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2015

Processing active devices on Si interposer and impact on cost.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013
Si interposer build-up options and impact on 3D system cost.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique.
IEEE Trans. Instrum. Meas., 2012

2011
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

Development of cost-effective biocompatible packaging for microelectronic devices.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

3D stacking using ultra thin dies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

3D integration: Circuit design, test, and reliability challenges.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.
Proceedings of the 15th European Test Symposium, 2010

Cost effectiveness of 3D integration options.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Effects of Parameter Variations on Timing Characteristics of Clocked Registers.
J. Circuits Syst. Comput., 2009

Impact of 3D design choices on manufacturing cost.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007
Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Power supply variation effects on timing characteristics of clocked registers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effects of crosstalk noise on H-tree clock distribution networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effects of process and environmental variations on timing characteristics of clocked registers.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers.
Proceedings of the Integrated Circuit and System Design, 2005

2004
Clock tree layout design for reduced delay uncertainty.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Buffer Sizing for Crosstalk Induced Delay Uncertainty.
Proceedings of the Integrated Circuit and System Design, 2004

Buffer sizing for delay uncertainty induced by process variations.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
Reduced Delay Uncertainty in High Performance Clock Distribution Networks.
Proceedings of the 2003 Design, 2003

2002
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling.
J. Circuits Syst. Comput., 2002

SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links.
Proceedings of the NETWORKING 2002, 2002

2001
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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