Stephan Wong

According to our database1, Stephan Wong authored at least 97 papers between 2000 and 2019.

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Bibliography

2019
CIM-SIM: Computation In Memory SIMuIator.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Memristive Device Based Circuits for Computation-in-Memory Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW Processor.
IEEE Trans. Multi-Scale Computing Systems, 2018

Increasing resource utilization in mixed-criticality systems using a polymorphic VLIW processor.
Journal of Systems Architecture - Embedded Systems Design, 2018

Evaluating Auto-adaptation Methods for Fine-Grained Adaptable Processors.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Using a polymorphic VLIW processor to improve schedulability and performance for mixed-criticality systems.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

Exploring ILP and TLP on a Polymorphic VLIW Processor.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility.
Signal Processing Systems, 2016

Leveraging Compiler Support on VLIW Processors for Efficient Power Gating.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Run-time phase prediction for a reconfigurable VLIW processor.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Adaptive ILP control to increase fault tolerance for VLIW processors.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal.
TRETS, 2015

Hierarchical SNR Scalable Video Coding with Adaptive Quantization for Reduced Drift Error.
Proceedings of the VISAPP 2015, 2015

Using VLIW softcore processors for image processing applications.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Evaluation of energy savings on a VLIW processor through dynamic issue-width adaptation.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Multiple contexts in a multi-ported VLIW register file implementation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A sparse VLIW instruction encoding scheme compatible with generic binaries.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Drift-free video coding for privacy protected video scrambling.
Proceedings of the 10th International Conference on Information, 2015

Using wavelet transform self-similarity for effective multiple description video coding.
Proceedings of the 10th International Conference on Information, 2015

2014
Multiple description coding for SNR scalable video transmission over unreliable networks.
Multimedia Tools Appl., 2014

Spatial Multiple Description Coding for Scalable Video Streams.
Int. J. Digital Multimedia Broadcasting, 2014

A run-time modulo scheduling by using a binary translation mechanism.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2013
A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Support for dynamic issue width in VLIW processors using generic binaries.
Proceedings of the Design, Automation and Test in Europe, 2013

Embedded Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

Configurable Fault-Tolerance for a Configurable VLIW Processor.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Unbalanced multiple description wavelet coding for scalable video transmission.
J. Electronic Imaging, 2012

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays.
IET Computers & Digital Techniques, 2012

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Adapting communication for adaptable processors: A multi-axis reconfiguration approach.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Task Scheduling in Large-scale Distributed Systems Utilizing Partial Reconfigurable Processing Elements.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

On Virtualization of Reconfigurable Hardware in Distributed Systems.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

Embedded reconfigurable architectures.
Proceedings of the 15th International Conference on Compilers, 2012

A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
A Cache Architecture for Counting Bloom Filters: Theory and Application.
J. Electrical and Computer Engineering, 2011

Collaboration of reconfigurable processors in grid computing: Theory and application.
Future Gener. Comput. Syst., 2011

Task scheduling strategies for dynamic reconfigurable processors in distributed systems.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

A Simulation Framework for Reconfigurable Processors in Large-Scale Distributed Systems.
Proceedings of the 2011 International Conference on Parallel Processing Workshops, 2011

Inverse Integer Transform in H.264/AVC Intra-frame Encoder.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2011

Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Design Trade-offs in Customized On-chip Crossbar Schedulers.
Signal Processing Systems, 2010

Cache-Based Memory Copy Hardware Accelerator for Multicore Systems.
IEEE Trans. Computers, 2010

An efficient realization of forward integer transform in H.264/AVC intra-frame encoder.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Special session on multicore architectures for embedded systems.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Modeling and Simulation of Reconfigurable Processors in Grid Networks.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

A shared reconfigurable VLIW multiprocessor system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Collaboration of Reconfigurable Processors in Grid Computing for Multimedia Kernels.
Proceedings of the Advances in Grid and Pervasive Computing, 5th International Conference, 2010

A multiported register file with register renaming for configurable softcore VLIW processors.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A VLIW softcore processor with dynamically adjustable issue-slots.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Configurable, low-power design for inverse integer transform in H.264/AVC.
Proceedings of the FIT '10, 2010

Dynamically reconfigurable register file for a softcore VLIW processor.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Design and performance evaluation of an adaptive FPGA for network applications.
Microelectronics Journal, 2009

Multiple Description Scalable Coding for Video Transmission over Unreliable Networks.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Introduction to the Future of Reconfigurable Computing and Processor Architectures.
Proceedings of the Embedded Computer Systems: Architectures, 2009

A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

A Drift-Reduced Hierarchical Wavelet Coding Scheme for Scalable Video Transmissions.
Proceedings of the First International Conference on Advances in Multimedia, 2009

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

K-Stage Pipelined Bloom Filter for Packet Classification.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs.
Parallel Processing Letters, 2008

Weighted Embedded Zero Tree for Scalable Video Compression.
Proceedings of the 2008 International Conference on Image Processing, 2008

A Paradigm for Reconfigurable Processing on Grid.
Proceedings of the Networks for Grid Applications, Second International Conference, 2008

A Memory-Optimized Bloom Filter Using an Additional Hashing Function.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

p-VEX: A reconfigurable and extensible softcore VLIW processor.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

An Approach for Optimal Bandwidth Allocation in Packet Processing Systems.
Proceedings of the Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 2008

Optimal Unroll Factor for Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Editorial.
Journal of Systems Architecture, 2007

Modified collision packet classification using counting bloom filter in tuple space.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

A Cache Architecture for Counting Bloom Filters.
Proceedings of the 15th IEEE International Conference on Networks, 2007

A Load/Store Unit for a Memcpy Hardware Accelerator.
Proceedings of the FPL 2007, 2007

Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro.
Proceedings of the FPL 2007, 2007

An OCM based shared Memory controller for Virtex 4.
Proceedings of the FPL 2007, 2007

Customizing Reconfigurable On-Chip Crossbar Scheduler.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, 2007

Systematic Customization of On-Chip Crossbar Interconnects.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
High-performance switching based on buffered crossbar fabrics.
Comput. Networks, 2006

A hardware cache memcpy accelerator.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Profiling Bluetooth and Linux on the Xilinx Virtex II Pro.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

The Molen FemtoJava Engine.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

PISC: Polymorphic Instruction Set Computers.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
A Reconfigurable Perfect-Hashing Scheme for Packet Inspection.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
The MOLEN Polymorphic Processor.
IEEE Trans. Computers, 2004

2003
Microcode Processing: Positioning and Directions.
IEEE Micro, 2003

2002
Microcoded Reconfigurable Embedded Processors: Current Developments.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Alternatives in FPGA-based SAD implementations.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

A Sum of Absolute Differences Implementation in FPGA Hardware.
Proceedings of the 28th EUROMICRO Conference 2002, 4-6 September 2002, Dortmund, Germany, 2002

2001
Coarse Reconfigurable Multimedia Unit Extension.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

The MOLEN rho-mu-Coded Processor.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
General-Purpose Processor Huffman Encoding Extension.
Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000

Multimedia Enhanced General-Purpose Processors.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000


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