Jianwang Zhai

According to our database, Jianwang Zhai authored at least 22 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits.

Shan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu, Jianwang Zhai, Chuan Shi, Wenjian Yu

CoRR, July, 2025

HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules.

Zixuan Li, Kanglin Tian, Jianwang Zhai, Zirui Li, Kang Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

MILS: Modality Interaction Driven Learning for Logic Synthesis.

Mingyu Zhao, Jiawei Liu, Jianwang Zhai, Chuan Shi

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design.

Zichao Ling, Lin Li, Yi Huang, Yixin Xuan, Jianwang Zhai, Kang Zhao

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction.

Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu, Bei Yu, Chuan Shi

Proceedings of the Design, Automation & Test in Europe Conference, 2025

IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning.

Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi

Proceedings of the Design, Automation & Test in Europe Conference, 2025

FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs.

Zirui Li, Kanglin Tian, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis.

Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

The Survey of 2.5D Integrated Architecture: An EDA perspective.

Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration.

Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong

ACM Trans. Design Autom. Electr. Syst., January, 2024

The Survey of Chiplet-based Integrated Architecture: An EDA perspective.

Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu

CoRR, 2024

Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing.

Zirui Li, Jianwang Zhai, Zixuan Li, Zhongdong Qi, Kang Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network.

Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing.

Feng Guo, Jiawei Liu, Jianwang Zhai, Jingyu Jia, Kang Zhao, Chuan Shi

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model.

Jingyu Jia, Jianwang Zhai, Kang Zhao

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.

Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

Microarchitecture Design Space Exploration via Pareto-Driven Active Learning.

Jianwang Zhai, Yici Cai

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.

Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning.

Jianwang Zhai, Yici Cai, Bei Yu

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2021

Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits.

Jianwang Zhai, Yici Cai, Qiang Zhou

IEEE Trans. Circuits Syst. II Express Briefs, 2021

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs.

Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.

Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021