Jing Guo

Orcid: 0000-0002-6434-5281

Affiliations:
  • North University of China, Science and Technology on Electronic Test and Measurement Laboratory, Taiyuan, China
  • Harbin Institute of Technology, Microelectronics Center, China (PhD 2015)


According to our database1, Jing Guo authored at least 18 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2022
A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS.
IEEE Trans. Emerg. Top. Comput., 2021

Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design.
IEEE Trans. Emerg. Top. Comput., 2021

High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets.
IEEE Trans. Aerosp. Electron. Syst., 2021

2020
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology.
IEEE Access, 2020

Self-Recovery Tolerance Latch Design Based on the Radiation Mechanism.
IEEE Access, 2020

2019
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Cost-Effective Relative Humidity Sensor Based on Side Coupling Induction Technology.
Sensors, 2017

2015
Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.
IEEE Trans. Reliab., 2015

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology.
Microelectron. Reliab., 2015

Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Fault Secure Encoder and Decoder Designs for Matrix Codes.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs.
IEEE Micro, 2013


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