Jonathan Woodruff

Orcid: 0000-0003-3971-2681

According to our database1, Jonathan Woodruff authored at least 20 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.
IEEE Des. Test, February, 2024

2023
The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System.
IEEE Micro, 2023

Towards xBGAS on CHERI: Supporting a Secure Global Memory.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Architectural Contracts for Safe Speculation.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2020

2019
CHERI Concentrate: Practical Compressed Capabilities.
IEEE Trans. Computers, 2019

Data transfer: A longitudinal analysis of clipboard and drag-and-drop use in desktop applications.
Int. J. Hum. Comput. Stud., 2019

CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

2017
Investigating the Use of a Dynamic Physical Bar Chart for Data Exploration and Presentation.
IEEE Trans. Vis. Comput. Graph., 2017


CHERI JNI: Sinking the Java Security Model into the C.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Lane Change and Merge Maneuvers for Connected and Automated Vehicles: A Survey.
IEEE Trans. Intell. Veh., 2016

Fast Protection-Domain Crossing in the CHERI Capability-System Architecture.
IEEE Micro, 2016

2015
CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization.
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
CHERI: a RISC capability machine for practical memory safety.
PhD thesis, 2014

The CHERI capability model: Revisiting RISC in an age of risk.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
A 64-bit MIPS processor running freebsd on a portable FPGA tablet.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013


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