Jörg Schreiter

Orcid: 0000-0001-9445-7084

According to our database1, Jörg Schreiter authored at least 16 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2020
Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

2019
How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2016

2004
An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation.
Proceedings of the Image Processing: Algorithms and Systems III, 2004

Pulse coupled neural networks with adaptive synapses for image segmentation.
Proceedings of the ARCS 2004, 2004

2003
CMOS image sensor with mixed-signal processor array.
IEEE J. Solid State Circuits, 2003

High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2002
Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity.
Proceedings of the 12th IEEE Workshop on Neural Networks for Signal Processing, 2002

An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights.
Proceedings of the Artificial Neural Networks, 2002

2001
A vision device for image processing.
Proceedings of the Signal and Image Processing (SIP 2001), 2001

Minimizing charge injection errors in high-precision, high-speed SC-circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
Design of parallel preprocessing image sensors.
Proceedings of the Third International Conference on Knowledge-Based Intelligent Information Engineering Systems, 1999


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