According to our database1, Benedikt Noethen authored at least 14 papers between 2012 and 2018.
Legend:Book In proceedings Article PhD thesis Other
A Hardware/Software Stack for Heterogeneous Systems.
IEEE Trans. Multi-Scale Computing Systems, 2018
A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.
Proceedings of the 54th Annual Design Automation Conference, 2017
A database accelerator for energy-efficient query processing and optimization.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
An MPSoC for energy-efficient database query processing.
Proceedings of the 53rd Annual Design Automation Conference, 2016
M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016
Untersuchungen von Kommunikationsmechanismen in heterogenen Mehrprozessorsystemen.
PhD thesis, 2015
Demo abstract: Taming many heterogeneous cores.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015
Query processing on low-energy many-core processors.
Proceedings of the 31st IEEE International Conference on Data Engineering Workshops, 2015
Towards dependable CPS infrastructures: Architectural and operating-system challenges.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs.
ACM Trans. Embedded Comput. Syst., 2014
CM_ISA++: An instruction set for dynamic task scheduling units for more than 1000 cores.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs.
Proceedings of the 2013 International Symposium on System on Chip, 2013
Towards elastic SDR architectures using dynamic task management.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012