Holger Eisenreich

According to our database, Holger Eisenreich authored at least 23 papers between 2009 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.

Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich

Proceedings of the 20th International SoC Design Conference, 2023

2021

IC Design & Technology Co-Development: e-NVM & mmWave enablement of 22FDX™ Technology.

Sabine Kolodinski, Holger Eisenreich, Steffen Lehmann, Johannes Müller

Proceedings of the International Conference on IC Design and Technology, 2021

2020

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology.

Sebastian Höppner, Holger Eisenreich, Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Jörg Schreiter, Thorsten Riedel, Heiner Bauer, Robert Niebsch, Stephan Scherzer, Thomas Hocker, Stefan Scholze, Stephan Henker, Matthias Nossmann, Ulrich Hensel, Helmut Prengel

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.

Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner

Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

2019

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.

Florian Schraut, Holger Eisenreich, Sebastian Höppner, Christian Mayr

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC.

Sebastian Höppner, Jörg Schreiter, Robert Niebsch, Stephan Scherzer, Ulrich Hensel, Jörg Winkler, Mario Orgis, Holger Eisenreich, Dennis Walter, Uwe Steeb, André Scharfe, Clifford Dmello, Robert Sinkwitz, Heiner Bauer, Alexander Oefelein, Florian Schraut

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2017

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology.

Heiner Bauer, Sebastian Höppner, Johannes Partzsch, Dennis Walter, Christian Mayr, Florian Schraut, Holger Eisenreich

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederström, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard P. Fettweis

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

An MPSoC for energy-efficient database query processing.

Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.

Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schluessler, Holger Eisenreich, René Schüffny

IEEE J. Solid State Circuits, 2015

A deep-submicron CMOS flow for general-purpose timing-detection insertion.

Andreas Dixius, Dennis Walter, Sebastian Höppner, Holger Eisenreich, René Schüffny

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014

10.7 A 105GOPS 36mm² heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.

Benedikt Noethen, Oliver Arnold, Esther P. Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, J.-U. Schlusler, Stefan Scholze, Dennis Walter, René Schüffny

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A compact on-chip IR-drop measurement system in 28 nm CMOS technology.

Sebastian Dietel, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stefan Hänzsche, Stephan Henker, René Schüffny, Tim Brauninger, Ulrich Fiedler

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology.

Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny

IEEE Trans. Very Large Scale Integr. Syst., 2013

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology.

Sebastian Höppner, Stefan Hänzsche, Georg Ellguth, Dennis Walter, Holger Eisenreich, René Schüffny

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology.

Sebastian Höppner, Dennis Walter, Holger Eisenreich, Stefan Schiefer, René Schüffny

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

A 32 GBit/s communication SoC for a waferscale neuromorphic system.

Stefan Scholze, Holger Eisenreich, Sebastian Höppner, Georg Ellguth, Stephan Henker, Mario Ander, Stefan Hänzsche, Johannes Partzsch, Christian Mayr, René Schüffny

Integr., 2012

A 335Mb/s 3.9mm² 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.

Markus Winter, Steffen Kunze, Esther P. Adeva, Björn Mennenga, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Sebastian Höppner, Stefan Scholze, René Schüffny, Tomoyoshi Kobori

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.

Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter, Gerhard P. Fettweis

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs.

Sebastian Höppner, Chenming Shao, Holger Eisenreich, Georg Ellguth, Mario Ander, René Schüffny

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010

Efficient compensation of delay variations in high-speed network-on-chip data links.

Sebastian Höppner, Dennis Walter, Holger Eisenreich, René Schüffny

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Low power design of the X-GOLD^® SDR 20 baseband processor.

Wolfgang Raab, Jörg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A novel ADPLL design using successive approximation frequency control.

Holger Eisenreich, Christian Mayr, Stephan Henker, Michael Wickert, René Schüffny

Microelectron. J., 2009