Friedrich Pauls

Orcid: 0000-0003-1508-0261

According to our database1, Friedrich Pauls authored at least 22 papers between 2013 and 2026.

Collaborative distances:

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
TEEM³: Core-Independent and Cooperating Trusted Execution Environments.
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

Reinforced Logic-Based Distributed Routing within Isolated Secure Zones.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing.
IEEE Trans. Very Large Scale Integr. Syst., October, 2025

A Multidimensional Hardware Trojan Design Platform to Enhance Hardware Security.
IEEE Embed. Syst. Lett., February, 2025

An Architectural Approach for the Secure Integration of Hardware Accelerators into a Trustworthy MPSoC Platform.
Proceedings of the 18th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2025

A Survey on Recent Developments in SCOAP-based Hardware Trojan Detection Strategies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Attack on Memory Encryption in MPSoCs using HT-infected AES core.
Proceedings of the 32nd IEEE International Conference on Electronics, Circuits and Systems, 2025

Secure AI Runtime System Based on the M3 Platform.
Proceedings of the 59th Asilomar Conference on Signals, 2025

2024
Trustworthy Silicon: An MPSoC for a Secure Operating System.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

Hardware Attack Models in Tiled Chip Multi-Core Processors: A Survey.
Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

Integration of IP-Cores for the M<sup>3</sup> Architecture with Low Area Overhead: Accelerator Support Module.
Proceedings of the 21st International SoC Design Conference, 2024

2023
Trust-minimized Integration of Third-Party Intellectual Property Cores.
Proceedings of the 20th International SoC Design Conference, 2023

2022
Trustworthy Computing for O-RAN: Security in a Latency-Sensitive Environment.
Proceedings of the IEEE Globecom 2022 Workshops, 2022

2021
Aspects of latency optimization for hash-based digital signatures.
PhD thesis, 2021

2019
Access Interval Prediction for Tightly Coupled Memory Systems.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2017
Modeling the Impact on Performance of Memory Pooling in Heterogeneous MPSoCs.
Proceedings of the 85th IEEE Vehicular Technology Conference, 2017


2016

2013
Evaluation of Efficient Modes of Operation of GSM/GPRS Modules for M2M Communications.
Proceedings of the 78th IEEE Vehicular Technology Conference, 2013

Towards elastic SDR architectures using dynamic task management.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013


  Loading...