Jouke Verbree

According to our database, Jouke Verbree authored at least 7 papers between 2010 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.

Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree

J. Electron. Test., 2012

2011

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs.

Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

A structured and scalable test access architecture for TSV-based 3D stacked ICs.

Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs.

Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen

Proceedings of the 2011 IEEE International Test Conference, 2010

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.

Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis

Proceedings of the 15th European Test Symposium, 2010

Test-architecture optimization for TSV-based 3D stacked ICs.

Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree

Proceedings of the 15th European Test Symposium, 2010

3D DfT architecture for pre-bond and post-bond testing.

Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg

Proceedings of the IEEE International Conference on 3D System Integration, 2010