Ju-Yueh Lee

According to our database, Ju-Yueh Lee authored at least 12 papers between 2006 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

In-place LUT polarity inVersion to mitigate soft errors for FPGAs.

Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2012

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.

Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He

ACM Trans. Design Autom. Electr. Syst., 2012

Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs.

Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011

In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults.

Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Mitigating FPGA interconnect soft errors by in-place LUT inversion.

Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.

Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fault modeling and characteristics of SRAM-based FPGAs (abstract only).

Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

In-place decomposition for robustness in FPGA.

Ju-Yueh Lee, Zhe Feng, Lei He

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications.

Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He

Proceedings of the Design, Automation and Test in Europe, 2010

Fault-tolerant resynthesis with dual-output LUTs.

Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.

Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2006

Low power scheduling method using multiple supply voltages.

Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006