Chun Zhang

Affiliations:
  • Xilinx, San Jose, CA, USA
  • Missouri University of Science and Technology, Rolla, MO, USA
  • Nanyang Technological University, School of Electrical and Electronic Engineering, Singapore
  • Fudan University, State Key Lab of ASIC and System, Shanghai, China (PhD 2011)


According to our database1, Chun Zhang authored at least 19 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

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Online presence:

On csauthors.net:

Bibliography

2016
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2014
Runtime Self-Calibrated Temperature-Stress Cosensor for 3-D Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014

On the Deployment of On-Chip Noise Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Variation aware optimal threshold voltage computation for on-chip noise sensors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

MSim: A general cycle accurate simulation platform for memcomputing studies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Fast Filter-Based Boolean Matchers.
IEEE Embed. Syst. Lett., 2013

Benchmarking for research in power delivery networks of three-dimensional integrated circuits.
Proceedings of the International Symposium on Physical Design, 2013

Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Eagle-eye: a near-optimal statistical framework for noise sensor placement.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors.
Proceedings of the Design, Automation and Test in Europe, 2013

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A novel memristor-based rSRAM structure for multiple-bit upsets immunity.
IEICE Electron. Express, 2012

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Fair energy resource allocation by minority game algorithm for smart buildings.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Fault modeling and characteristics of SRAM-based FPGAs (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Accelerating Boolean Matching Using Bloom Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Engineering a scalable Boolean matching based on EDA SaaS 2.0.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Building a faster boolean matcher using bloom filter.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010


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