Juan C. Moure

According to our database1, Juan C. Moure authored at least 45 papers between 1994 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Bibliography

2018
High Throughput Image Codec for High-Resolution Satellite Images.
Proceedings of the 2018 IEEE International Geoscience and Remote Sensing Symposium, 2018

2017
GPU Implementation of Bitplane Coding with Parallel Coefficient Processing for High Performance Image Compression.
IEEE Trans. Parallel Distrib. Syst., 2017

Introducing computational thinking, parallel programming and performance engineering in interdisciplinary studies.
J. Parallel Distrib. Comput., 2017

Coalition structure generation problems: optimization and parallelization of the IDP algorithm in multicore systems.
Concurrency and Computation: Practice and Experience, 2017

GPU-Accelerated Real-Time Stixel Computation.
Proceedings of the 2017 IEEE Winter Conference on Applications of Computer Vision, 2017

Slanted Stixels: Representing San Francisco's Steepest Streets.
Proceedings of the British Machine Vision Conference 2017, 2017

2016
Bitplane Image Coding With Parallel Coefficient Processing.
IEEE Trans. Image Processing, 2016

Embedded Real-time Stereo Estimation via Semi-Global Matching on the GPU.
Proceedings of the International Conference on Computational Science 2016, 2016

GPU-based Pedestrian Detection for Autonomous Driving.
Proceedings of the International Conference on Computational Science 2016, 2016

2015
Implementation of the DWT in a GPU through a Register-based Strategy.
IEEE Trans. Parallel Distrib. Syst., 2015

Boosting the FM-Index on the GPU: Effective Techniques to Mitigate Random Memory Access.
IEEE/ACM Trans. Comput. Biology Bioinform., 2015

Strategies of SIMD Computing for Image Coding in GPU.
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

Teaching Parallel Programming in Interdisciplinary Studies.
Proceedings of the Euro-Par 2015: Parallel Processing Workshops, 2015

Strategy of Microscopic Parallelism for Bitplane Image Coding.
Proceedings of the 2015 Data Compression Conference, 2015

Parallelisation and Application of AD 3 as a Method for Solving Large Scale Combinatorial Auctions.
Proceedings of the Coordination Models and Languages, 2015

Paving the way for Large-Scale Combinatorial Auctions.
Proceedings of the 2015 International Conference on Autonomous Agents and Multiagent Systems, 2015

2014
Improving the Execution Performance of FreeSurfer - A New Scheduled Pipeline Scheme for Optimizing the Use of CPU and GPU Resources.
Neuroinformatics, 2014

FM-Index on GPU: A Cooperative Scheme to Reduce Memory Footprint.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Thread-cooperative, bit-parallel computation of levenshtein distance on GPU.
Proceedings of the 2014 International Conference on Supercomputing, 2014

Job scheduling in Hadoop with Shared Input Policy and RAMDISK.
Proceedings of the 2014 IEEE International Conference on Cluster Computing, 2014

2013
Job scheduling for optimizing data locality in Hadoop clusters.
Proceedings of the 20th European MPI Users's Group Meeting, 2013

An Optimization for MapReduce Frameworks in Multi-core Architectures.
Proceedings of the International Conference on Computational Science, 2013

n-step FM-Index for Faster Pattern Matching.
Proceedings of the International Conference on Computational Science, 2013

msPar: A Parallel Coalescent Simulator.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

2012
Analysis and improvement of map-reduce data distribution in read mapping applications.
The Journal of Supercomputing, 2012

2011
Performance Behavior Prediction Scheme for Shared-Memory Parallel Applications.
Proceedings of the 2011 IEEE International Conference on Cluster Computing (CLUSTER), 2011

2010
Active learning processes to study memory hierarchy on Multicore systems.
Proceedings of the International Conference on Computational Science, 2010

Selecting a Suitable Multicore System for Shared-memory Parallel Applications.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2010

A reconfigurable cache memory with heterogeneous banks.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
High-speed network modeling for full system simulation.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

2007
Adaptive L2 Cache for Chip Multiprocessors.
Proceedings of the Euro-Par 2007 Workshops: Parallel Processing, 2007

2006
Wide and efficient trace prediction using the local trace predictor.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Evaluation of the field-programmable cache: performance and energy consumption.
Proceedings of the Third Conference on Computing Frontiers, 2006

A Reconfigurable Data Cache for Adaptive Processors.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Performance and Power Evaluation of an Intelligently Adaptive Data Cache.
Proceedings of the High Performance Computing, 2005

Target Encoding for Efficient Indirect Jump Prediction.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

2004
Graduate students learning strategies through research collaboration.
Proceedings of the 9th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2004

2003
Optimizing a Decoupled Front-End Architecture: The Indexed Fetch Target Buffer (iFTB).
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
The KScalar simulator.
ACM Journal of Educational Resources in Computing, 2002

Speeding Up Target Address Generation Using a Self-indexed FTB (Research Note).
Proceedings of the Euro-Par 2002, 2002

2001
Improving Single-Thread Fetch Performance on a Multithreaded Processor.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

1999
Scalable simultaneous multithreading (ScSMT).
Proceedings of the Parallel Computing: Fundamentals & Applications, 1999

1996
TransCom: A Communication Microkernel for Transputers.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

1994
Programming environment for a transputer based computer.
Future Generation Comp. Syst., 1994

Transputer Based System Software.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994


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