Juho Kim

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2025
WACA-UNet: Weakness-Aware Channel Attention for Static IR Drop Prediction in Integrated Circuit Design.
CoRR, July, 2025

Evaluations at Work: Measuring the Capabilities of GenAI in Use.
CoRR, May, 2025

Investigating Large Language Models in Diagnosing Students' Cognitive Skills in Math Problem-solving.
CoRR, April, 2025

PokerKit: A Comprehensive Python Library for Fine-Grained Multivariant Poker Game Simulations.
IEEE Trans. Games, March, 2025

An LLM-Integrated Framework for Completion, Management, and Tracing of STPA.
CoRR, March, 2025

Empirical Validation of the Independent Chip Model.
Proceedings of the IEEE Conference on Games, 2025

2024
Temporal-Feature-Based Classification of Active Sonar Targets in a Deep-Water Environment.
IEEE Trans. Aerosp. Electron. Syst., October, 2024

Observing the Southern US Culture of Honor Using Large-Scale Social Media Analysis.
CoRR, 2024

GPU-Accelerated Counterfactual Regret Minimization.
CoRR, 2024

LearnerVoice: A Dataset of Non-Native English Learners' Spontaneous Speech.
Proceedings of the 25th Annual Conference of the International Speech Communication Association, 2024

Recording and Describing Poker Hands.
Proceedings of the IEEE Conference on Games, 2024

2023
The Tacotron-Based Signal Synthesis Method for Active Sonar.
Sensors, 2023

Poker Hand History File Format Specification.
CoRR, 2023

PadChannel: Improving CNN Performance through Explicit Padding Encoding.
CoRR, 2023

PokerKit: A Comprehensive Python Library for Fine-Grained Multi-Variant Poker Game Simulations.
CoRR, 2023

2022
Delay Impact on Process Variation of Interconnect throughout technology scaling.
Proceedings of the 19th International SoC Design Conference, 2022

High-Level Synthesis Considering Layer Assignment on Timing in 3D-IC.
Proceedings of the 19th International SoC Design Conference, 2022

BTI-Aware Cell Characterization based on Neural Network.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2020
Detecting evolutionary patterns of cancers using consensus trees.
Bioinform., 2020

Symmetrical Buffered Clock Tree Synthesis Considering NBTI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2019

2018
Teaching Syntax by Adversarial Distraction.
Proceedings of the First Workshop on Fact Extraction and VERification, 2018

2017
Kapre: On-GPU Audio Preprocessing Layers for a Quick Implementation of Deep Neural Network Models with Keras.
CoRR, 2017

Scalable Visualization for High-dimensional Single-cell Data.
Proceedings of the Biocomputing 2017: Proceedings of the Pacific Symposium, 2017

Enhanced Misuse Cases for Prioritization of Security Requirements.
Proceedings of the 9th International Conference on Information Management and Engineering, Barcelona, Spain, October 09, 2017

2016
Performance optimization in FinFET-based circuit using TILOS-like gate sizing.
Proceedings of the International Symposium on Integrated Circuits, 2016

Organic Crowdsourcing Systems.
Proceedings of the 2016 AAAI Spring Symposia, 2016

2014
Implementation of a Rotational Ultrasound Biomicroscopy System Equipped with a High-Frequency Angled Needle Transducer - <i>Ex Vivo</i> Ultrasound Imaging of Porcine Ocular Posterior Tissues.
Sensors, 2014

SERA: a secure energy reliability aware data gathering for sensor networks.
Multim. Tools Appl., 2014

Cost effective data wiping methods for mobile phone.
Multim. Tools Appl., 2014

Ensemble algorithms for DNA motif finding.
Proceedings of the International Conference on Electronics, Information and Communications, 2014

Ensemble learning for robust prediction of microRNA-mRNA interactions.
Proceedings of the International Conference on Big Data and Smart Computing, BIGCOMP 2014, 2014

2013
Variation-Aware Aging Analysis in Digital ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Performance and Usability Aware Secure Two-Factor User Authentication Scheme for Wireless Sensor Networks.
Int. J. Distributed Sens. Networks, 2013

DDoS avoidance strategy for service availability.
Clust. Comput., 2013

Toolscape: enhancing the learning experience of how-to videos.
Proceedings of the 2013 ACM SIGCHI Conference on Human Factors in Computing Systems, 2013

2012
Confidential information protection system for mobile devices.
Secur. Commun. Networks, 2012

A Security-Performance-Balanced User Authentication Scheme for Wireless Sensor Networks.
Int. J. Distributed Sens. Networks, 2012

Selective Application of VPN by Service Using Port Number in SSL-Based Host-to-Gateway VPN Environment.
Proceedings of the Convergence and Hybrid Information Technology, 2012

2011
Security Requirements Prioritization Based on Threat Modeling and Valuation Graph.
Proceedings of the Convergence and Hybrid Information Technology, 2011

Specification-Based Intrusion Detection System for WiBro.
Proceedings of the Convergence and Hybrid Information Technology, 2011

Statistical aging analysis with process variation consideration.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
JTAG Security System Based on Credentials.
J. Electron. Test., 2010

NBTI-aware statistical timing analysis framework.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2008
Efficient cell characterization for SSTA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Stochastic glitch elimination considering path correlation.
Proceedings of the 2007 IEEE International SOC Conference, 2007

2006
Stochastic Glitch Estimation and Path Balancing for Statistical Optimization.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2002
Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
Proceedings of ASP-DAC 2001, 2001

1998
Interleaving buffer insertion and transistor sizing into a single optimization.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Performance optimization by gate sizing and path sensitization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

CADIC: computer-aided design on internet with cryptosystem.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

Combined transistor sizing with buffer insertion for timing optimization.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs.
Proceedings of the 1997 International Symposium on Physical Design, 1997


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