Taigon Song

According to our database1, Taigon Song authored at least 19 papers between 2011 and 2020.

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Bibliography

2020
Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm.
IEEE Access, 2020

2017
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits.
J. Inform. and Commun. Convergence Engineering, 2015

Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs.
J. Inform. and Commun. Convergence Engineering, 2015

Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

2011
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Signal integrity analysis and optimization for 3D ICs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC.
Proceedings of the 48th Design Automation Conference, 2011


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