Taigon Song

Orcid: 0000-0001-5243-4132

According to our database1, Taigon Song authored at least 37 papers between 2011 and 2023.

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Bibliography

2023
T<sup>3</sup>L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023

NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023

Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

HFGCN: High-speed and Fully-optimized GCN Accelerator.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond.
Proceedings of the 20th International SoC Design Conference, 2023

High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture.
Proceedings of the 20th International SoC Design Conference, 2023

2022
Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory.
Proceedings of the 19th International SoC Design Conference, 2022

Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021
An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs).
Proceedings of the 18th International SoC Design Conference, 2021

A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

NS3K: A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm.
IEEE Access, 2020

A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption.
Proceedings of the International SoC Design Conference, 2020

2017
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits.
J. Inform. and Commun. Convergence Engineering, 2015

Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs.
J. Inform. and Commun. Convergence Engineering, 2015

Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

2011
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Signal integrity analysis and optimization for 3D ICs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC.
Proceedings of the 48th Design Automation Conference, 2011


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