Jun-Ho Choy

According to our database, Jun-Ho Choy authored at least 11 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects.

Jun-Ho Choy, Stéphane Moreau, Catherine Brunet-Manquat, Valeriy Sukharev, Armen Kteyan

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution.

Armen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun-Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stéphane Moreau

Proceedings of the 2023 International Symposium on Physical Design, 2023

2022

Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids.

Valeriy Sukharev, Armen Kteyan, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Jun-Ho Choy, Sofya Torosyan, Yu Zhu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance.

Armen Kteyan, Jun-Ho Choy, Valeriy Sukharev, Massimo Bertoletti, Carmelo Maiorca, Rossana Zadra, Massimo Inzaghi, Gabriele Gattere, Giancarlo Zinco, Paolo Valente, Roberto Bardelli, Alessandro Valerio, Pierluigi Rolandi, Mattia Monetti, Valentina Cuomo, Salvatore Santapa

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2019

Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages.

Armen Kteyan, Henrik Hovsepyan, Jun-Ho Choy, Valeriy Sukharev

Proceedings of the IEEE International Reliability Physics Symposium, 2019

An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems.

Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2016

Electromigration assessment for power grid networks considering temperature and thermal stress effects.

Xin Huang, Valeriy Sukharev, Jun-Ho Choy, Marko Chew, Taeyoung Kim, Sheldon X.-D. Tan

Integr., 2016

2015

Post placement leakage reduction with stress-enhanced filler cells.

Jun-Ho Choy, Valeriy Sukharev, Armen Kteyan, Henrik Hovsepyan, Ramnath Venkatraman, Ruggero Castagnetti

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014

Accurate full-chip estimation of power map, current densities and temperature for EM assessment.

Marko Chew, Ara Aslyan, Jun-Ho Choy, Xin Huang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2012

Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance.

Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy, Henrik Hovsepyan, Ara Markosian, Ehrenfried Zschech, Rene Huebner

J. Electron. Test., 2012

2009

Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation.

Valeriy Sukharev, Ara Markosian, Armen Kteyan, Levon Manukyan, Nikolay Khachatryan, Jun-Ho Choy, Hasmik Lazaryan, Henrik Hovsepyan, Seiji Onoue, Takuo Kikuchi, Tetsuya Kamigaki

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009