Ping-Sheng Wu
Orcid: 0009-0007-7825-9599
According to our database1,
Ping-Sheng Wu authored at least 8 papers
between 2014 and 2026.
Collaborative distances:
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Bibliography
2026
A 40-nm 209-TOPS/W Reinforcement Learning Processor With Full Speculation Exploitation and Inference-Training Parallel Processing.
IEEE J. Solid State Circuits, March, 2026
30.5 A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 22nm 96Mb 50.6-to-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device.
IEEE J. Solid State Circuits, January, 2025
A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 22 nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications.
IEEE Trans. Circuits Syst. Artif. Intell., September, 2024
A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-Based Speculation.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2014
Using Heritage Risk Maps as an Approach for Estimating the Climate Impact to Cultural Heritage Materials in the Island of Taiwan.
Proceedings of the Digital Heritage. Progress in Cultural Heritaage: Documentation, Preservation, and Protection, 2014