Kaiyuan Guo

According to our database1, Kaiyuan Guo authored at least 21 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Towards Lower Bit Multiplication for Convolutional Neural Network Training.
CoRR, 2020

Enable Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Soft Error Mitigation for Deep Convolution Neural Network on FPGA Accelerators.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
[DL] A Survey of FPGA-based Neural Network Inference Accelerators.
ACM Trans. Reconfigurable Technol. Syst., 2019

Compressed CNN Training with FPGA-based Accelerator.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2018

Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RRAM Based Buffer Design for Energy Efficient CNN Accelerator.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Efficient Reconfigurable Framework for General Purpose CNN-RNN Models on FPGAs.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Real-time object detection towards high power efficiency.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Software-Hardware Codesign for Efficient Neural Network Acceleration.
IEEE Micro, 2017

A Survey of FPGA Based Neural Network Accelerator.
CoRR, 2017

Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

From model to FPGA: Software-hardware co-design for efficient neural network acceleration.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Real-Time Pedestrian Detection and Tracking on Customized Hardware.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

2015
An FPGA-based real-time simultaneous localization and mapping system.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

2014
A universal FPGA-based floating-point matrix processor for mobile systems.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014


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