Jie Wang

Orcid: 0000-0002-2133-7943

Affiliations:

University of California, Computer Science Department, Los Angeles, CA, USA
Tsinghua University, Beijing, China

According to our database¹, Jie Wang authored at least 28 papers between 2015 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2023

TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., December, 2023

FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., June, 2023

Democratizing Domain-Specific Computing.

[BibT_eX]

[DOI]

Commun. ACM, 2023

Grape: Practical and Efficient Graphed Execution for Dynamic Deep Neural Networks on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

A Comprehensive Automated Exploration Framework for Systolic Array Designs.

[BibT_eX]

[DOI]

Suhail Basalama

Jie Wang

Jason Cong

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

RapidStream: Parallel Physical Implementation of FPGA HLS Designs.

[BibT_eX]

[DOI]

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021

Automatic Synthesis and Architecture Optimization of Systolic Arrays.

[BibT_eX]

[DOI]

Jie Wang

PhD thesis, 2021

Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned.

[BibT_eX]

[DOI]

Jie Wang

Jason Cong

CoRR, 2021

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Extending High-Level Synthesis for Task-Parallel Programs.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA.

[BibT_eX]

[DOI]

Jie Wang

Licheng Guo

Jason Cong

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Extending High-Level Synthesis for Task-Parallel Programs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

UNIT: Unifying Tensorized Instruction Compilation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

2020

FLASH: Fast, Parallel, and Accurate Simulator for HLS.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization.

[BibT_eX]

[DOI]

CoRR, 2020

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs.

[BibT_eX]

[DOI]

Christopher J. Hughes

Pradeep Dubey

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

End-to-End Optimization of Deep Learning Applications.

[BibT_eX]

[DOI]

Atefeh Sohrabizadeh

Jie Wang

Jason Cong

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency.

[BibT_eX]

[DOI]

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit.

[BibT_eX]

[DOI]

Mau-Chung Frank Chang

Jason Cong

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Rapid Cycle-Accurate Simulator for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

PolySA: polyhedral-based systolic array auto-compilation.

[BibT_eX]

[DOI]

Jason Cong

Jie Wang

Proceedings of the International Conference on Computer-Aided Design, 2018

Automatic Interior I/O Elimination in Systolic Array Architecture.

[BibT_eX]

[DOI]

Jason Cong

Jie Wang

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms.

[BibT_eX]

[DOI]

Jie Wang

Xinfeng Xie

Jason Cong

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only).

[BibT_eX]

[DOI]

Jie Wang

Jason Cong

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Jie Wang

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