According to our database1, Katell Morin-Allory authored at least 38 papers between 2003 and 2020.
Legend:Book In proceedings Article PhD thesis Other
FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
Mining Missing Assumptions from Counter-Examples.
ACM Trans. Embedded Comput. Syst., 2019
A Distributed Body-Biasing Strategy for Asynchronous Circuits.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Comparison of Synchronous and Asynchronous FIR Filter Architectures.
Proceedings of the 5th International Conference on Event-Based Control, 2019
Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017
Extraction of missing formal assumptions in under-constrained designs.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Conclusively verifying clock-domain crossings in very large hardware designs.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Clock domain crossing formal verification: a meta-model.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016
Efficient and Correct by Construction Assertion-Based Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Enabler-based synchronizer model for clock domain crossing static verification.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015
SyntHorus-2: Automatic prototyping from PSL.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Fast prototyping from assertions: A pragmatic approach.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013
C-elements for Hardened Self-timed Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Does asynchronous technology bring robustness in synchronous circuit monitoring?
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
Formal Verification of C-element Circuits.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010
Synthesis of asynchronous monitors for critical electronic systems.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Delay Insensitivity Does Not Mean Slope Insensitivity!
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010
From Assertion-Based Verification to Assertion-Based Synthesis.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
MYGEN: automata-based on-line test generator for assertion-based verification.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
RAT-based formal verification of QDI asynchronous controllers.
Proceedings of the Forum on specification and Design Languages, 2009
High-level symbolic simulation for automatic model extraction.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Assertion-Based Design with Horus.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008
Proving and disproving assertion rewrite rules with automated theorem provers.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Synthesis of Property Monitors for Online Fault Detection.
Journal of Circuits, Systems, and Computers, 2007
Asynchronous online-monitoring of logical and temporal assertions.
Proceedings of the Forum on specification and Design Languages, 2007
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
On-Line Test Vector Generation from Temporal Constraints Written in PSL.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Asynchronous Assertion Monitors for multi-Clock Domain System Verification.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006
On-line Monitoring of Properties Built on Regular Expressions.
Proceedings of the Forum on specification and Design Languages, 2006
Proven correct monitors from PSL specifications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Verification of safety properties for parameterized regular systems.
ACM Trans. Embedded Comput. Syst., 2005
A proof of correctness for the construction of property monitors.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic.
Proceedings of the Correct Hardware Design and Verification Methods, 2005
Vérification Formelle dans le Modèle Polyédrique. (Formal Verification in the Polyhedral Model).
PhD thesis, 2004
Verification of Control Properties in the Polyhedral Model.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003