Sylvain Engels

According to our database1, Sylvain Engels authored at least 19 papers between 2006 and 2019.

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Bibliography

2019
A Digital Event-Based Strategy for ASK demodulation.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Distributed Body-Biasing Strategy for Asynchronous Circuits.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

An Event-Based Strategy for ASK demodulation.
Proceedings of the 5th International Conference on Event-Based Control, 2019

2018
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI.
J. Low Power Electronics, 2018

A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits.
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017
Event-based design strategy for circuit electromagnetic compatibility.
Proceedings of the 3rd International Conference on Event-Based Control, 2017

2014
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.
J. Solid-State Circuits, 2014

Clockless Design Performance Monitoring for Nanometer Technologies.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013


2011
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Bottom-up digital system-level reliability modeling.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
On-Chip Process Variability Monitoring Flow.
J. Low Power Electronics, 2010

2009
Timing margin evaluation with a simple statistical timing analysis flow.
J. Embedded Computing, 2009

Product On-Chip Process Compensation for Low Power and Yield Enhancement.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2007
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
Logical effort model extension to propagation delay representation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects.
Integr., 2006

Statistical Characterization of Library Timing Performance.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006


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