Katsuhiro Seta

According to our database, Katsuhiro Seta authored at least 6 papers between 1991 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.

Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama

IEEE J. Solid State Circuits, 2006

2005

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction.

Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa

Proceedings of the 2005 Design, 2005

2002

Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications.

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Automated selective multi-threshold design for ultra-low standby applications.

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1992

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file.

Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba

IEEE J. Solid State Circuits, November, 1992

1991

0.5- mu m 2 M-transistor BiPNMOS channelless gate array.

Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe

IEEE J. Solid State Circuits, November, 1991