Shinichiro Shiratake

According to our database1, Shinichiro Shiratake authored at least 12 papers between 2006 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Session 30 overview: Emerging memories: Memory and technology directions subcommittees.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

F1: Intelligent energy-efficient systems at the edge of IoT.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs.
IEEE J. Solid State Circuits, 2015

2011
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.
IEEE J. Solid State Circuits, 2011

2010
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
IEEE J. Solid State Circuits, 2010


2009

2006
Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI.
IEICE Trans. Electron., 2006

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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