Kuniaki Koyama

According to our database, Kuniaki Koyama authored at least 6 papers between 1990 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2003

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.

Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama

IEEE J. Solid State Circuits, 2003

2000

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.

Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda

IEEE J. Solid State Circuits, 2000

1996

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.

Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda

IEEE J. Solid State Circuits, 1996

1995

A 1-Gb DRAM for file applications.

Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, Kentaro Shibahara, Ryuichi Oikawa, Hidemitsu Mori, Shouichi Iwao, Tatsunori Murotani, Kuniaki Koyama, Shinichi Fukuzawa, Toshiro Itani, Kunihiko Kasama, Takashi Okuda, Shuichi Ohya, Masaki Ogawa

IEEE J. Solid State Circuits, November, 1995

1992

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.

Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda

IEEE J. Solid State Circuits, November, 1992

1990

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM.

Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama

IEEE J. Solid State Circuits, August, 1990