Kuo-Liang Cheng

According to our database1, Kuo-Liang Cheng authored at least 19 papers between 2000 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2007
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2005
Design and test of a scalable security processor.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
An SOC Test Integration Platform and Its Industrial Realization.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Test and Diagnosis of Word-Oriented Multiport Memories.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Fault Pattern Oriented Defect Diagnosis for Memories.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAME: A Fault-Pattern Based Memory Failure Analysis Framework.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Fault simulation and test algorithm generation for random accessmemories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Flash Memory Built-In Self-Test Using March-Like Algorithm.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Scheduling of BISTed Memory Cores for SOC.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

March-based RAM diagnosis algorithms for stuck-at and coupling faults.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.
Proceedings of the 38th Design Automation Conference, 2001

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Simulation-Based Test Algorithm Generation for Random Access Memories.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Error Catch and Analysis for Semiconductor Memories Using March Tests.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000


  Loading...