Jing-Reng Huang

According to our database1, Jing-Reng Huang authored at least 16 papers between 1999 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2007
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2004
A Built-In Parametric Timing Measurement Unit.
IEEE Des. Test Comput., 2004

An SOC Test Integration Platform and Its Industrial Realization.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Test Scheduling of BISTed Memory Cores for SOC.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A built-in timing parametric measurement unit.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A low-cost CMOS time interval measurement core.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
BRAINS: A BIST Compiler for Embedded Memories.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

An FPGA-based re-configurable functional tester for memory chips.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A realistic fault model for flash memories.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A programmable built-in self-test core for embedded memories.
Proceedings of ASP-DAC 2000, 2000

1999
A Programmable BIST Core for Embedded DRAM.
IEEE Des. Test Comput., 1999


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