Jing-Reng Huang

According to our database, Jing-Reng Huang authored at least 16 papers between 1999 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

STEAC: A Platform for Automatic SOC Test Integration.

Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2007

2004

A Built-In Parametric Timing Measurement Unit.

Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang

IEEE Des. Test Comput., 2004

An SOC Test Integration Platform and Its Industrial Realization.

Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002

Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.

Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Test Scheduling of BISTed Memory Cores for SOC.

Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Scheduling and Test Access Architecture Optimization for System-on-Chip.

Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses.

Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs.

Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A built-in timing parametric measurement unit.

Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A low-cost CMOS time interval measurement core.

Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.

Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

BRAINS: A BIST Compiler for Embedded Memories.

Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

An FPGA-based re-configurable functional tester for memory chips.

Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A realistic fault model for flash memories.

Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A programmable built-in self-test core for embedded memories.

Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu

Proceedings of ASP-DAC 2000, 2000

1999

A Programmable BIST Core for Embedded DRAM.

Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang

IEEE Des. Test Comput., 1999