Kyumin Kwon

According to our database, Kyumin Kwon authored at least 8 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 1/10 DTC Range Reduction Technique in a Fractional-N MDLL Using a Reference Triggered Ring Oscillator.

Kyumin Kwon, Yaswanth Kumar Cherivirala, David D. Wentzloff

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2023

PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter.

Kyumin Kwon, Omar A. B. Abdelatty, David D. Wentzloff

IEEE J. Solid State Circuits, May, 2023

An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer.

Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn

IEEE J. Solid State Circuits, 2023

Synthesizable ADPLL Generator: From Specification to GDS.

Kyumin Kwon, David D. Wentzloff

Proceedings of the 19th International Conference on Synthesis, 2023

2022

A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates.

Hyochan An, Samuel R. Nason-Tomaszewski, Jongyup Lim, Kyumin Kwon, Matthew S. Willsey, Parag G. Patil, Hun-Seok Kim, Dennis Sylvester, Cynthia A. Chestek, David T. Blaauw

IEEE Trans. Biomed. Circuits Syst., 2022

An 81.6dB SNDR 15.625MHz BW 3^rd Order CT SDM with a True TI NS Quantizer.

Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.

Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff

Proceedings of the VLSI-SoC: Design Trends, 2020

An Open-source Framework for Autonomous SoC Design with Analog Block Generation.

Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020