Lang Feng

Orcid: 0000-0001-9943-0550

Affiliations:
  • Sun Yat-Sen University, Shenzhen, China


According to our database1, Lang Feng authored at least 22 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2025
A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline.
ACM Trans. Design Autom. Electr. Syst., July, 2025

PreSIT: Predict Cryptography Computations in SGX-Style Integrity Trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

A High Efficient and Scalable Obstacle-Avoiding VLSI Global Routing Flow.
CoRR, March, 2025

CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Hybrid Exact and Heuristic Efficient Transistor Network Optimization for Multi-Output Logic.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

An MIP-based Force-directed Large Scale Placement Refinement Algorithm.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender.
IEEE Trans. Computers, June, 2024

Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins.
ACM Trans. Design Autom. Electr. Syst., March, 2024

RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices.
IEEE Trans. Computers, February, 2024

A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA.
IACR Cryptol. ePrint Arch., 2024

A Rule-Based High Efficient Obstacle-Avoiding RSMT Algorithm for VLSI Routing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Hardware-Assisted Control-Flow Integrity Enhancement for IoT Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
ProMiSE: A High-Performance Programmable Hardware Monitor for High Security Enforcement of Software Execution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design.
ACM Trans. Design Autom. Electr. Syst., 2023

2022
Toward Taming the Overhead Monster for Data-flow Integrity.
ACM Trans. Design Autom. Electr. Syst., 2022

RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity.
IEEE Trans. Computers, 2022

2021
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation.
ACM Trans. Design Autom. Electr. Syst., 2021

2020
How Much Does Regularity Help FPGA Placement?
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
Layout recognition attacks on split manufacturing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Exploring Serverless Computing for Neural Network Training.
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2017
Making split fabrication synergistically secure and manufacturable.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017


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