Laura Tosoratto
According to our database1,
Laura Tosoratto
authored at least 25 papers
between 2010 and 2022.
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Bibliography
2022
Architectural improvements and technological enhancements for the APEnet+ interconnect system.
CoRR, 2022
2016
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
J. Syst. Archit., 2016
Proceedings of the IEEE International Symposium on Systems Engineering, 2016
2015
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Gener. Comput. Syst., 2015
A hierarchical watchdog mechanism for systemic fault awareness on distributed systems.
Future Gener. Comput. Syst., 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes.
CoRR, 2014
NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features.
CoRR, 2014
Proceedings of the 33rd IEEE International Symposium on Reliable Distributed Systems, 2014
EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster.
CoRR, 2013
Applications of Many-Core Technologies to On-line Event Reconstruction in High Energy Physics Experiments.
CoRR, 2013
NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.
CoRR, 2013
A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.
CoRR, 2013
Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.
CoRR, 2013
'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems.
CoRR, 2013
Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
2012
The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture
CoRR, 2012
2011
APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters
CoRR, 2011
2010
APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters
CoRR, 2010