Francesco Simula

According to our database1, Francesco Simula
  • authored at least 22 papers between 2010 and 2017.
  • has a "Dijkstra number"2 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017

2016
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
Journal of Systems Architecture - Embedded Systems Design, 2016

2015
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Generation Comp. Syst., 2015

A hierarchical watchdog mechanism for systemic fault awareness on distributed systems.
Future Generation Comp. Syst., 2015

Scaling to 1024 software processes and hardware cores of the distributed simulation of a spiking neural network including up to 20G synapses.
CoRR, 2015

Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses.
CoRR, 2015

Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores.
CoRR, 2015

2014
EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes.
CoRR, 2014

NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features.
CoRR, 2014

LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System.
Proceedings of the 33rd IEEE International Symposium on Reliable Distributed Systems, 2014

2013
Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster.
CoRR, 2013

NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.
CoRR, 2013

A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.
CoRR, 2013

Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.
CoRR, 2013

'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems.
CoRR, 2013

GPU peer-to-peer techniques applied to a cluster interconnect.
CoRR, 2013

Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

GPU Peer-to-Peer Techniques Applied to a Cluster Interconnect.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture
CoRR, 2012

2011
APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters
CoRR, 2011

2010
APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters
CoRR, 2010


  Loading...