Francesco Simula

Orcid: 0000-0002-7955-1491

According to our database1, Francesco Simula authored at least 38 papers between 2010 and 2023.

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In proceedings 
PhD thesis 


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Two-compartment neuronal spiking model expressing brain-state specific apical-amplification, -isolation and -drive regimes.
CoRR, 2023

APEIRON: composing smart TDAQ systems for high energy physics experiments.
CoRR, 2023

Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach.
Microprocess. Microsystems, November, 2022

Fast Simulation of a Multi-Area Spiking Network Model of Macaque Cortex on an MPI-GPU Cluster.
Frontiers Neuroinformatics, August, 2022

NREM and REM: cognitive and energetic effects in thalamo-cortical sleeping and awake spiking model.
CoRR, 2022

Architectural improvements and technological enhancements for the APEnet+ interconnect system.
CoRR, 2022

Fast Simulations of Highly-Connected Spiking Cortical Models Using GPUs.
Frontiers Comput. Neurosci., 2021

A new GPU library for fast simulation of large-scale networks of spiking neurons.
CoRR, 2020

Performance and Energy Footprint Assessment of FPGAs and GPUs on HPC Systems Using Astrophysics Application.
Comput., 2020

Scaling of a large-scale simulation of synchronous slow-wave and asynchronous awake-like activity of a cortical model with long-range interconnections.
CoRR, 2019

Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.
Microprocess. Microsystems, 2018

Gaussian and Exponential Lateral Connectivity on Distributed Spiking Neural Network Simulation.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States.
Proceedings of the Parallel Computing is Everywhere, 2017

Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects.
Proceedings of the Parallel Computing is Everywhere, 2017

Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
J. Syst. Archit., 2016

ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Gener. Comput. Syst., 2015

A hierarchical watchdog mechanism for systemic fault awareness on distributed systems.
Future Gener. Comput. Syst., 2015

Scaling to 1024 software processes and hardware cores of the distributed simulation of a spiking neural network including up to 20G synapses.
CoRR, 2015

Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses.
CoRR, 2015

Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores.
CoRR, 2015

EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes.
CoRR, 2014

NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features.
CoRR, 2014

LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System.
Proceedings of the 33rd IEEE International Symposium on Reliable Distributed Systems, 2014

Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster.
CoRR, 2013

NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.
CoRR, 2013

A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.
CoRR, 2013

Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.
CoRR, 2013

'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems.
CoRR, 2013

Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

GPU Peer-to-Peer Techniques Applied to a Cluster Interconnect.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture
CoRR, 2012

APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters
CoRR, 2011

APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters
CoRR, 2010