Piero Vicini

According to our database1, Piero Vicini authored at least 23 papers between 1993 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Bibliography

2018
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

Gaussian and Exponential Lateral Connectivity on Distributed Spiking Neural Network Simulation.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

2017
Power-Efficient Computing: Experiences from the COSA Project.
Scientific Programming, 2017

MiniSymposium on Energy Aware Scientific Computing on Low Power and Heterogeneous Architectures.
Proceedings of the Parallel Computing is Everywhere, 2017


The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States.
Proceedings of the Parallel Computing is Everywhere, 2017

Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects.
Proceedings of the Parallel Computing is Everywhere, 2017


2016

2015
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Generation Comp. Syst., 2015

A hierarchical watchdog mechanism for systemic fault awareness on distributed systems.
Future Generation Comp. Syst., 2015

2014
LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System.
Proceedings of the 33rd IEEE International Symposium on Reliable Distributed Systems, 2014

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

2013
Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

GPU Peer-to-Peer Techniques Applied to a Cluster Interconnect.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2009
Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

2006
Computing for LQCD: apeNEXT.
Computing in Science and Engineering, 2006

SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2004
APENet: a high speed, low latency 3D interconnect network.
Proceedings of the 2004 IEEE International Conference on Cluster Computing (CLUSTER 2004), 2004

2003

1997

1993
The APE-100 Computer: (I) the Architecture.
International Journal of High Speed Computing, 1993


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