Iuliana Bacivarov

According to our database1, Iuliana Bacivarov authored at least 40 papers between 2002 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
Journal of Systems Architecture - Embedded Systems Design, 2016

EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes.
CoRR, 2014

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Reliability-aware mapping optimization of multi-core systems with mixed-criticality.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

AdaPNet: Adapting process networks in response to resource variations.
Proceedings of the 2014 International Conference on Compilers, 2014

Predictability for timing and temperature in multiprocessor system-on-chip platforms.
ACM Trans. Embedded Comput. Syst., 2013

Real-time worst-case temperature analysis with temperature-dependent parameters.
Real-Time Systems, 2013

Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs.
J. Electronic Testing, 2013

EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment
CoRR, 2013

Reliable and Efficient Execution of Multiple Streaming Applications on Intel's SCC Processor.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Designing Applications with Predictable Runtime Characteristics for the Baremetal Intel SCC.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism.
Proceedings of the International Conference on Compilers, 2013

Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications.
ACM Trans. Embedded Comput. Syst., 2012

Worst-case temperature analysis for different resource models.
IET Circuits, Devices & Systems, 2012

Worst-Case Temperature Guarantees for Real-Time Applications on Multi-core Systems.
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

Fast worst-case peak temperature evaluation for real-time applications on multi-core systems.
Proceedings of the 13th Latin American Test Workshop, 2012

Multi-objective mapping optimization via problem decomposition for many-core systems.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Scenario-based design flow for mapping streaming applications onto on-chip many-core systems.
Proceedings of the 15th International Conference on Compilers, 2012

Power agnostic technique for efficient temperature estimation of multicore embedded systems.
Proceedings of the 15th International Conference on Compilers, 2012

Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Thermal-Aware Task Assignment for Real-Time Applications on Multi-Core Systems.
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status.
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

Worst-case temperature analysis for real-time systems.
Proceedings of the Design, Automation and Test in Europe, 2011

Thermal-aware system analysis and software synthesis for embedded multi-processors.
Proceedings of the 48th Design Automation Conference, 2011

Mapping of applications to MPSoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip.
Proceedings of the Handbook of Signal Processing Systems, 2010

A modular fast simulation framework for stream-oriented MPSoC.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

Generation and calibration of compositional performance analysis models for multi-processor systems.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

Scalably distributed SystemC simulation for embedded applications.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

Mapping Applications to Tiled Multiprocessor Embedded Systems.
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

ChronoSym: a new approach for fast and accurate SoC cosimulation.
IJES, 2005

Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer.
Proceedings of the 2003 Design, 2003

Multi-Level Software Validation for NoC.
Proceedings of the Networks on Chip, 2003

Timed HW-SW cosimulation using native execution of OS and application SW.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002