Letian Huang

Orcid: 0000-0003-3907-9150

According to our database1, Letian Huang authored at least 44 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
360-GS: Layout-guided Panoramic Gaussian Splatting For Indoor Roaming.
CoRR, 2024

On the Error Analysis of 3D Gaussian Splatting and an Optimal Projection Strategy.
CoRR, 2024

2023
Detection of Thermal Covert Channel Attacks Based on Classification of Components of the Thermal Signal Features.
IEEE Trans. Computers, April, 2023

Modeling and Analysis of Thermal Covert Channel Attacks in Many-core Systems.
IEEE Trans. Computers, February, 2023

Self-NeRF: A Self-Training Pipeline for Few-Shot Neural Radiance Fields.
CoRR, 2023

2022
Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Detection of and Countermeasure Against Thermal Covert Channel in Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Design Challenges of Intrachiplet and Interchiplet Interconnection.
IEEE Des. Test, 2022

On Evaluation of On-chip Thermal Covert Channel Attacks.
Proceedings of the International Conference on Compilers, 2022

2021
Runtime Performance Optimization of 3-D Microprocessors in Dark Silicon.
IEEE Trans. Computers, 2021

ECDR$^{2}$2: Error Corrector and Detector Relocation Router for Network-on-Chip.
IEEE Trans. Computers, 2021

An enhanced planned obsolescence attack by aging networks-on-chip.
J. Syst. Archit., 2021

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective.
IEEE Access, 2021

A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators.
Proceedings of the NANOCOM '21: The Eighth Annual ACM International Conference on Nanoscale Computing and Communication, Virtual Event, Italy, September 7, 2021

2020
Combating Enhanced Thermal Covert Channel in Multi-/Many-Core Systems With Channel-Aware Jamming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

On Countermeasures Against the Thermal Covert Channel Attacks Targeting Many-core Systems.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Efficient Design-for-Test Approach for Networks-on-Chip.
IEEE Trans. Computers, 2019

Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system.
Integr., 2019

Testing aware dynamic mapping for path-centric network-on-chip test.
Integr., 2019

Online Path-Based Test Method for Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Optimizing dynamic mapping techniques for on-line NoC test.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.
Microprocess. Microsystems, 2017

Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A low latency fault tolerant transmission mechanism for Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An energy efficient approach for C4.5 algorithm using OpenCL design flow.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Non-Blocking Testing for Network-on-Chip.
IEEE Trans. Computers, 2016

Tolerating transient illegal turn faults in NoCs.
Microprocess. Microsystems, 2016

An efficient FPGA implementation for odd-even sort based KNN algorithm using OpenCL.
Proceedings of the International SoC Design Conference, 2016

A lightweight metric for the evaluation of network congestion in NoC-based MPSoC.
Proceedings of the International SoC Design Conference, 2016

Neural network based seizure detection system using raw EEG data.
Proceedings of the International SoC Design Conference, 2016

An address remapping algorithm to reduce power consumption in NoC-based chip-multiprocessors.
Proceedings of the International SoC Design Conference, 2016

VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

Optimizing the location of ECC protection in network-on-chip.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems.
IEEE Embed. Syst. Lett., 2015

Fault-resilient routing unit in NoCs.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Design of Fault-Tolerant and Reliable Networks-on-Chip.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

An Efficient KNN Algorithm Implemented on FPGA Based Heterogeneous Computing System Using OpenCL.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Rescuing healthy cores against disabled routers.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers.
Proceedings of the IEEE 11th International Conference on Dependable, 2013


  Loading...