Yarui Peng

Orcid: 0000-0002-8550-2063

According to our database1, Yarui Peng authored at least 19 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Design Challenges of Intrachiplet and Interchiplet Interconnection.
IEEE Des. Test, 2022

2021
Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2017
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2004
A Framework of Total Performance Improvement and Transaction Cost-driven Business Process Outsourcing Strategy.
Proceedings of the Pacific Asia Conference on Information Systems, 2004


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