Lennart Bamberg
Orcid: 0000-0003-4673-8310
According to our database1,
Lennart Bamberg
authored at least 33 papers
between 2016 and 2023.
Collaborative distances:
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Bibliography
2023
IEEE Trans. Parallel Distributed Syst., April, 2023
2022
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs.
ACM Trans. Model. Comput. Simul., 2022
ARTS: An adaptive regularization training schedule for activation sparsity exploration.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2021
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021
Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies.
Proceedings of the NANOCOM '21: The Eighth Annual ACM International Conference on Nanoscale Computing and Communication, Virtual Event, Italy, September 7, 2021
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Integr., 2020
IEEE Comput. Archit. Lett., 2020
Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Micro, 2019
Simulation environment for link energy estimation in networks-on-chip with virtual channels.
Integr., 2019
Integr., 2019
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment.
Integr., 2019
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs.
CoRR, 2019
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures.
IEEE Access, 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
Integr., 2018
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Misalignment-aware delay modeling of narrow on-chip interconnects considering variability.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016