Luca Colagrande

According to our database, Luca Colagrande authored at least 12 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization.

Luca Colagrande, Luca Benini

IEEE Trans. Parallel Distributed Syst., June, 2025

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration.

Luca Colagrande, Lorenzo Leone, Maximilian Coco, Andrei Deaconeasa, Luca Benini

CoRR, June, 2025

FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators.

Chi Zhang, Luca Colagrande, Renzo Andri, Thomas Benz, Gamze Islamoglu, Alessandro Nadalini, Francesco Conti, Yawei Li, Luca Benini

CoRR, May, 2025

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.

Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini

IEEE J. Solid State Circuits, April, 2025

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores.

Luca Colagrande, Luca Benini

CoRR, March, 2025

A Multicast-Capable AXI Crossbar for Many-core Machine Learning Accelerators.

Luca Colagrande, Luca Benini

CoRR, February, 2025

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.

Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini

CoRR, January, 2025

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors.

Luca Colagrande, Jayanth Jonnalagadda, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024

Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform.

Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini

CoRR, 2024

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.

Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Optimizing Offload Performance in Heterogeneous MPSoCs.

Luca Colagrande, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers.

Paul Scheffler, Luca Colagrande, Luca Benini

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024