Marco Rios

According to our database, Marco Rios authored at least 13 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Overflow-free Compute Memories for Edge AI Acceleration.

Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza

ACM Trans. Embed. Comput. Syst., October, 2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference.

Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza

IEEE Trans. Emerg. Top. Comput., 2023

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication.

Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

2022

A Hardware/Software Co-Design Vision for Deep Learning at the Edge.

Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza

IEEE Micro, 2022

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge.

Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs.

Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing.

Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

BLADE: An in-Cache Computing Architecture for Edge Devices.

William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza

IEEE Trans. Computers, 2020

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.

Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal

IEEE Access, 2020

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems.

Alexandre Levisse, Marco Rios, Miguel Peón Quirós, David Atienza

Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures.

Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication.

Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Functionality Enhanced Memories for Edge-AI Embedded Systems.

Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza

Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019