Miguel Peón Quirós
Orcid: 0000-0002-5760-090X
According to our database1,
Miguel Peón Quirós
authored at least 30 papers
between 2005 and 2024.
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Bibliography
2024
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators.
CoRR, 2024
2023
Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems.
IEEE Trans. Computers, September, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Special Session: Challenges and Opportunities for Sustainable Multi-Scale Computing Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devices.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022
2021
Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors.
IEEE Trans. Emerg. Top. Comput., 2021
E<sup>2</sup>CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices.
IEEE Trans. Computers, 2021
2020
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Modular Design and Optimization of Biomedical Applications for Ultralow Power Heterogeneous Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices.
IEEE Des. Test, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
2019
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing.
IEEE Embed. Syst. Lett., 2019
Results from running an experiment as a service platform for mobile broadband networks in Europe.
Comput. Commun., 2019
2018
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the 11th Workshop on Wireless Network Testbeds, 2017
Experience: An Open Platform for Experimentation with Commercial Mobile Broadband Networks.
Proceedings of the 23rd Annual International Conference on Mobile Computing and Networking, 2017
2016
Proceedings of the 17th IEEE International Symposium on A World of Wireless, 2016
MONROE, a distributed platform to measure and assess mobile broadband networks: demo.
Proceedings of the Tenth ACM International Workshop on Wireless Network Testbeds, 2016
2015
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2015
Proceedings of the 2015 ACM Conference on Special Interest Group on Data Communication, 2015
Proceedings of the Sixth ACM Symposium on Cloud Computing, 2015
2010
Software metadata: Systematic characterization of the memory behaviour of dynamic applications.
J. Syst. Softw., 2010
2009
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.
J. Embed. Comput., 2009
2008
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
2006
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005