Miguel Peón Quirós

According to our database1, Miguel Peón Quirós authored at least 16 papers between 2005 and 2019.

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Bibliography

2019
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing.
Embedded Systems Letters, 2019

Results from running an experiment as a service platform for mobile broadband networks in Europe.
Comput. Commun., 2019

2018
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Results from Running an Experiment as a Service Platform for Mobile Networks.
Proceedings of the 11th Workshop on Wireless Network Testbeds, 2017

Experience: An Open Platform for Experimentation with Commercial Mobile Broadband Networks.
Proceedings of the 23rd Annual International Conference on Mobile Computing and Networking, 2017

2016

MONROE, a distributed platform to measure and assess mobile broadband networks: demo.
Proceedings of the Tenth ACM International Workshop on Wireless Network Testbeds, 2016

2015
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2015

Toward Automated Testing of Geo-Distributed Replica Selection Algorithms.
Computer Communication Review, 2015

The nearest replica can be farther than you think.
Proceedings of the Sixth ACM Symposium on Cloud Computing, 2015

2010
Software metadata: Systematic characterization of the memory behaviour of dynamic applications.
Journal of Systems and Software, 2010

2009
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.
J. Embedded Computing, 2009

2008
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005


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