William Andrew Simon

Orcid: 0000-0001-7357-7204

Affiliations:
  • École Polytechnique Fédérale de Lausanne, Vaud, Switzerland


According to our database1, William Andrew Simon authored at least 17 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2022
HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space Exploration.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Gem5-X: A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization.
ACM Trans. Archit. Code Optim., 2021

Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
BLADE: An in-Cache Computing Architecture for Edge Devices.
IEEE Trans. Computers, 2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2019
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms.
Proceedings of the 2019 Spring Simulation Conference, 2019

Functionality Enhanced Memories for Edge-AI Embedded Systems.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

BLADE: A BitLine Accelerator for Devices on the Edge.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Thermal characterization of next-generation workloads on heterogeneous MPSoCs.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Single-FPGA complete 3D and 2D medical ultrasound imager.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
Single-FPGA 3D ultrasound beamformer.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Demo: Efficient delay and apodization for on-FPGA 3D ultrasound.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016


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