Marc Bocquet
Orcid: 0000-0003-2675-0347
According to our database1,
Marc Bocquet
authored at least 65 papers
between 2008 and 2024.
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Bibliography
2024
Online model error correction with neural networks: application to the Integrated Forecasting System.
CoRR, 2024
2023
Machine Learning With Data Assimilation and Uncertainty Quantification for Dynamical Systems: A Review.
IEEE CAA J. Autom. Sinica, June, 2023
Surrogate modeling for the climate sciences dynamics with machine learning and data assimilation.
Frontiers Appl. Math. Stat., February, 2023
Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell.
CoRR, 2023
Memory Window in Si: HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes.
Proceedings of the IEEE International Memory Workshop, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Online model error correction with neural networks in the incremental 4D-Var framework.
CoRR, 2022
Voltage-Dependent Synaptic Plasticity (VDSP): Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential.
CoRR, 2022
1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing.
Proceedings of the IEEE International Memory Workshop, 2022
2021
Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A comparison of combined data assimilation and machine learning methods for offline and online model error correction.
J. Comput. Sci., 2021
Frontiers Appl. Math. Stat., 2021
State, global and local parameter estimation using local ensemble Kalman filters: applications to online machine learning of chaotic dynamics.
CoRR, 2021
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks.
CoRR, 2021
CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
2020
SIAM/ASA J. Uncertain. Quantification, 2020
Combining data assimilation and machine learning to emulate a dynamical model from sparse and noisy observations: A case study with the Lorenz 96 model.
J. Comput. Sci., 2020
Using machine learning to correct model error in data assimilation and forecast applications.
CoRR, 2020
Bayesian inference of dynamics from partial and noisy observations using data assimilation and machine learning.
CoRR, 2020
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.
IEEE Access, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
On the Efficiency of Covariance Localisation of the Ensemble Kalman Filter Using Augmented Ensembles.
Frontiers Appl. Math. Stat., 2019
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays.
CoRR, 2019
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks.
CoRR, 2019
IEEE Access, 2019
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction.
Microelectron. Reliab., 2018
Asymptotic Forecast Uncertainty and the Unstable Subspace in the Presence of Additive Model Error.
SIAM/ASA J. Uncertain. Quantification, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
Degenerate Kalman Filter Error Covariances and Their Convergence onto the Unstable Subspace.
SIAM/ASA J. Uncertain. Quantification, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014
J. Parallel Distributed Comput., 2014
Printed complementary organic thin film transistors based decoder for ferroelectric memory.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Microelectron. Reliab., 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
2012
J. Low Power Electron., 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
2011
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Design challenges for prototypical and emerging memory concepts relying on resistance switching.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2008
Simul. Model. Pract. Theory, 2008