Mathieu Moreau

Hussein Bazzi

Adnan Harb

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.

[BibT_eX]

[DOI]

César Fuguet Tortolero

Eric Guthmuller

Jean-Michel Portal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.

[BibT_eX]

[DOI]

IEEE Access, 2020

An Energy-Efficient Current-Controlled Write and Read Scheme for Resistive RAMs (RRAMs).

[BibT_eX]

[DOI]

IEEE Access, 2020

Design of a Novel Hybrid CMOS Non-Volatile SRAM Memory in 130nm RRAM Technology.

[BibT_eX]

[DOI]

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Resistive RAM SET and RESET Switching Voltage Evaluation as an Entropy Source for Random Number Generation.

[BibT_eX]

[DOI]

Hussein Bazzi

Hassen Aziza

Adnan Harb

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

True random number generation exploiting SET voltage variability in resistive RAM memory arrays.

[BibT_eX]

[DOI]

Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

An Augmented OxRAM Synapse for Spiking Neural Network (SNN) Circuits.

[BibT_eX]

[DOI]

Hassen Aziza

Hussein Bazzi

Pierre Canet

Adnan Harb

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

2018

Reliable ReRAM-based Logic Operations for Computing in Memory.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Design of Hybrid CMOS Non-Volatile SRAM Cells in 130nm RRAM Technology.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Microelectronics, 2018

Novel RRAM CMOS Non-Volatile Memory Cells in 130nm Technology.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on Computer and Applications (ICCA), 2018

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017

Architecture, design and technology guidelines for crosspoint memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

High density emerging resistive memories: What are the limits?

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Multilevel operation in oxide based resistive RAM with SET voltage modulation.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.

[BibT_eX]

[DOI]

Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

2014

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

A novel test structure for OxRRAM process variability evaluation.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2013

Synchronous full-adder based on complementary resistive switching memory cells.

[BibT_eX]

[DOI]

Yue Zhang

Erya Deng

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.

[BibT_eX]

[DOI]