Elisa Vianello
Orcid: 0000-0002-8868-9951
According to our database1,
Elisa Vianello
authored at least 74 papers
between 2010 and 2023.
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Bibliography
2023
DenRAM: Neuromorphic Dendritic Architecture with RRAM for Efficient Temporal Processing with Delays.
CoRR, 2023
Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell.
CoRR, 2023
CoRR, 2023
1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Dendritic Computation through Exploiting Resistive Memory as both Delays and Weights.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Neuromorph. Comput. Eng., 2022
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy.
Adv. Intell. Syst., 2022
Hardware calibrated learning to compensate heterogeneity in analog RRAM-based Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing.
Proceedings of the IEEE International Memory Workshop, 2022
Frequency modulation of conductance level in PCM device for neuromorphic applications.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks.
CoRR, 2021
Ex Situ Transfer of Bayesian Neural Networks to Resistive Memory-Based Inference Hardware.
Adv. Intell. Syst., 2021
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration.
IEEE Access, 2021
CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors.
Proceedings of the IEEE International Memory Workshop, 2021
Proceedings of the International Conference on IC Design and Technology, 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2020
In-situ learning harnessing intrinsic resistive memory variability through Markov Chain Monte Carlo Sampling.
CoRR, 2020
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.
IEEE Access, 2020
Analog Weight Updates with Compliance Current Modulation of Binary ReRAMs for On-Chip Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays.
CoRR, 2019
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks.
CoRR, 2019
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Insect-Inspired Elementary Motion Detection Embracing Resistive Memory and Spiking Neural Networks.
Proceedings of the Biomimetic and Biohybrid Systems - 7th International Conference, 2018
Role of synaptic variability in spike-based neuromorphic circuits with unsupervised learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural Networks.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Processing EMG signals using reservoir computing on an event-based neuromorphic system.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
Correlated Effects on Forming and Retention of Al Doping in HfO<sub>2</sub>-Based RRAM.
IEEE Des. Test, 2017
Bioinspired Programming of Resistive Memory Devices for Implementing Spiking Neural Networks.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Advances in the understanding of microscopic switching mechanisms in ReRAM devices (Invited paper).
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Real-time decoding of brain activity by embedded Spiking Neural Networks using OxRAM synapses.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Design considerations for reliable OxRAM-based non-volatile flip-flops in 28nm FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Impact of Si/Al implantation on the forming voltage and pre-forming conduction modes in HfO2 based OxRAM cells.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
On the impact of OxRAM-based synapses variability on convolutional neural networks performance.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Emerging resistive memories for low power embedded applications and neuromorphic systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Benefit of Al2O3/HfO2 bilayer for BEOL RRAM integration through 16kb memory cut characterization.
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Back-end 3D integration of HfO2-based RRAMs for low-voltage advanced IC digital design.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
On the forming-free operation of HfOx based RRAM devices: Experiments and ab initio calculations.
Proceedings of the European Solid-State Device Research Conference, 2013
Understanding the conduction mechanism of the chalcogenide Ag2S silver-doped through ab initio simulation.
Proceedings of the European Solid-State Device Research Conference, 2013
A novel HfO2-GeS2-Ag based conductive bridge RAM for reconfigurable logic applications.
Proceedings of the European Solid-State Device Research Conference, 2013
2012
On the impact of Ag doping on performance and reliability of GeS2-based Conductive Bridge Memories.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2010
PhD thesis, 2010