Markus Ulbricht

Orcid: 0000-0001-9230-640X

Affiliations:
  • IHP - Leibniz-Institut für innovative Mikroelektronik, Frankfurt/Oder, Germany
  • Brandenburg University of Technology, Cottbus, Germany


According to our database1, Markus Ulbricht authored at least 22 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

On csauthors.net:

Bibliography

2024
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

2023
Towards Reconfigurable CNN Accelerator for FPGA Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.
Proceedings of the High Performance Computing, 2023

Adaptive Lock-Step System for Resilient Multiprocessing Architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

PULP Fiction No More - Dependable PULP Systems for Space.
Proceedings of the IEEE European Test Symposium, 2023


Bits, Flips and RISCs.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
FPGA-Based Acceleration of Convolutional Neural Network for Gesture Recognition Using mm-Wave FMCW Radar.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

A Methodology for Identifying Critical Sequential Circuits with Graph Convolutional Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Machine Learning Approach for Accelerating Simulation-based Fault Injection.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
Fault Tolerant Platform for Communication and Distance Measurement in Highly Automated Driving.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Recognition of Objects in the Urban Environment using R-CNN and YOLO Deep Learning Algorithms.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

2019
Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor Processing.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Power/Area-Optimized Fault Tolerance for Safety Critical Applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

A Methodology to Verify Digital IP's within Mixed-Signal Systems.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2013
Virtual TMR Schemes Combining Fault Tolerance and Self Repair.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

On the feasibility of combining on-line-test and self repair for logic circuits.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Activity Migration in M-of-N-Systems by Means of Load-Balancing.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Combining on-line fault detection and logic self repair.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011


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