Maurizio Damiani

According to our database1, Maurizio Damiani authored at least 30 papers between 1988 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Partially unate Boolean functions: Properties of their sum-of-products representations.
Discret. Appl. Math., October, 2023

2003
Boolean Technology Mapping Based on Logic Decomposition.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2000
Enabling testability of fault-tolerant circuits by means of I<sub>DDQ</sub>-checkable voters.
IEEE Trans. Very Large Scale Integr. Syst., 2000

1999
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits.
Proceedings of the 36th Conference on Design Automation, 1999

1997
The state reduction of nondeterministic finite-state machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

The disjunctive decomposition of logic functions.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Scheduling and control generation with environmental constraints based on automata representations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Synthesis of Self-Testing Finite State Machines from High-Level Specifications.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Boolean Function Representation Based on Disjoint-Support Decompositions.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Boolean Function Representation Using Parallel-Access Diagrams.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
Proceedings of the Dependable Computing, 1996

1995
Optimization of combinational logic circuits based on compatible gates.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Reliability evaluation of combinational logic circuits by symbolic simulation.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis of combinational circuits with special fault-handling capabilitie.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis of multilevel fault-tolerant combinational circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
A Synthesis Framework Based on Trace and Automata Theory.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Scheduling with Environmental Constraints based on Automata Representations.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Nondeterministic finite-state machines and sequential <i>don't cares</i>.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Don't care set specifications in combinational and synchronous logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
Testability measures in pseudorandom testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Recurrence Equations and the Optimization of Synchronous Logic Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1991
Fault simulation of unconventional faults in CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Analysis and Design of Linear Finite State Machines for Signature Analysis Testing.
IEEE Trans. Computers, 1991

1990
Aliasing in signature analysis testing with multiple input shift registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Observability Don't Care Sets and Boolean Relations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
An analytical model for the aliasing probability in signature analysis testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing.
Proceedings of the Proceedings International Test Conference 1989, 1989

CMOS Design for Improved IC Testability.
Proceedings of the Proceedings International Test Conference 1989, 1989

Improved testability evaluations in combinational logic networks.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
Aliasing errors in signature analysis testing of integrated circuits.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988


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