Michael Riepen

According to our database, Michael Riepen authored at least 8 papers between 2010 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Enabling Computation Intensive Applications in Battery-Operated Cyber-Physical Systems.

Hans C. Woithe, William Brozas, Christian Wills, Bharath Pichai, Ulrich Kremer, Mike Eichhorn, Michael Riepen

Proceedings of the 6th Many-core Applications Research Community (MARC) Symposium. Proceedings of the 6th MARC Symposium, 2012

Connecting the Cloud: Transparent and Flexible Communication for a Cluster of Intel SCCs.

Pablo Reble, Carsten Clauss, Michael Riepen, Stefan Lankes, Thomas Bemmerl

Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, 2012

Invasive MPI on Intel's Single-Chip Cloud Computer.

Isaías A. Comprés Ureña, Michael Riepen, Michael Konow, Michael Gerndt

Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.

Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart

IEEE J. Solid State Circuits, 2011

SCC: A Flexible Architecture for Many-Core Platform Research.

Matthias Gries, Ulrich Hoffmann, Michael Konow, Michael Riepen

Comput. Sci. Eng., 2011

RCKMPI - Lightweight MPI Implementation for Intel's Single-chip Cloud Computer (SCC).

Isaías A. Comprés Ureña, Michael Riepen, Michael Konow

Proceedings of the Recent Advances in the Message Passing Interface, 2011

2010

The 48-core SCC Processor: the Programmer's View.

Timothy G. Mattson, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram R. Vangal, Nitin Borkar, Gregory Ruhl, Saurabh Dighe

Proceedings of the Conference on High Performance Computing Networking, 2010

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS.

Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson

Proceedings of the IEEE International Solid-State Circuits Conference, 2010