Vasantha Erraguntla

According to our database, Vasantha Erraguntla authored at least 18 papers between 2002 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

F3: Adaptive design techniques for energy efficiency.

Eric Fluhr, Michael Polley, Se-Hyun Yang, Vasantha Erraguntla, Tobias Noll, Kees van Berkel

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Split-Path Fused Floating Point Multiply Accumulate (FPMAC).

Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla

Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2012

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.

Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Vasant Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar

Proceedings of the 25th International Conference on VLSI Design, 2012

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.

Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An IA-32 processor with a wide voltage operating range in 32nm CMOS.

Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2011

A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.

Praveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Vasant Hoskote, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar

IEEE J. Solid State Circuits, 2011

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.

Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart

IEEE J. Solid State Circuits, 2011

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar

IEEE J. Solid State Circuits, 2011

2010

A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.

Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS.

Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS.

Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS.

Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.

Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar

IEEE J. Solid State Circuits, 2008

A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.

Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2004

Design Challenges in Sub-100nm High Performance Microprocessors.

Siva G. Narendra, Vasantha Erraguntla, James W. Tschanz, Nitin Borkar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS.

Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar

IEEE J. Solid State Circuits, 2003

2002

5-GHz 32-bit integer execution core in 130-nm dual-V_T CMOS.

Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar

IEEE J. Solid State Circuits, 2002