Howard Wilson

According to our database1, Howard Wilson authored at least 9 papers between 2001 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012


2010

2008
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.
IEEE J. Solid State Circuits, 2008

2007
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2003
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS.
IEEE J. Solid State Circuits, 2003

2002
5-GHz 32-bit integer execution core in 130-nm dual-V<sub>T</sub> CMOS.
IEEE J. Solid State Circuits, 2002

2001
A six-port 30-GB/s nonblocking router component using point-to-point simultaneous bidirectional signaling for high-bandwidth interconnects.
IEEE J. Solid State Circuits, 2001


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