Yatin Vasant Hoskote

According to our database1, Yatin Vasant Hoskote authored at least 20 papers between 1992 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2012
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.
Proceedings of the 25th International Conference on VLSI Design, 2012

2011
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.
IEEE J. Solid State Circuits, 2011

2010
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010


2009
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.
IEEE J. Solid State Circuits, 2008

Guest Editors' Introduction: Tackling Key Problems in NoCs.
IEEE Des. Test Comput., 2008

2006
A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization.
IEEE J. Solid State Circuits, 2006

2003
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS.
IEEE J. Solid State Circuits, 2003

1999
Coverage Estimation for Symbolic Model Checking.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Abstraction Techniques for Validation Coverage Analysis and Test Generation.
IEEE Trans. Computers, 1998

1997
Automatic verification of implementations of large circuits against HDL specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996
A Unified Framework for Design Validation and Manufacturing Test.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

1995
Verification of transient response of linear analog circuits.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Automated verification of temporal properties specified as state machines in VHDL.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
Verification of Circuits Described in VHDL through Extraction of Design Intent.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Abstraction of data path registers for multilevel verification of large circuits.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1992
Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems.
IEEE Trans. Computers, 1992


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